Memory Packages Having Stair Step Interconnection Layers

ABSTRACT

Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/381,357 filed on May 2, 2006, which is a continuation-in-part of U.S.patent application Ser. No. 10/987,187, filed on Nov. 12, 2004, now U.S.Pat. No. 7,388,279, which claims the benefit of U.S. ProvisionalApplication 60/519, 945 filed Nov. 12, 2003, and of U.S. ProvisionalApplication 60/676,863, filed May 2, 2005, all of which are incorporatedby reference in their entirety herein.

FIELD OF THE INVENTION

The present invention relates to the field of high speed electronicinterconnections for memory and the packaging of semiconductorintegrated circuits for use therewith.

BACKGROUND

Memory integrated circuits “ICs” for use with most computers operate atspeeds slower than current generation central processing unit “CPU” ICscreating a condition generally referred to as the “memory bottleneck”.In such condition, the CPU must remain in a wait state until the memorydata is written or retrieved. The problem has been addressed, in part,by improved memory system designs. However as electronic systems moveinto the multi-gigabit per second data rate range, a significant gapremains between top-end operating rates of CPU ICs and memory ICs. Partof this ongoing disparity is due to the limits of currentinterconnection design, which often results, particularly at higherfrequencies, in disturbances that contribute to signal distortion. Forexample, signal distortion can often be due, at least in part toso-called parasitic effects resulting from traditional interconnectdesigns. Because signal speed and signal integrity are two primary goalsin digital signal transmission, interconnect designs that assure signalintegrity during data transmission are key. Controlling signal integritybegins with the design of the circuit. Choices made in terms of circuitlayout, and the materials used and the general architecture of thecomplete assembly, will all have impact of the quality if the signaltransmission and its ultimate integrity.

Because parasitic effects and signal discontinuity are primary sourcesof signal disturbance, one of the major objectives in maintaining signalintegrity is to eliminate or minimize the parasitic effects andelectrical discontinuities impinging upon a signal. Parasitic effectsand electrical discontinuities are caused by a number of factors such assharp changes in direction, changes in material, circuit feature flawsand even interconnections, such as solder balls used to connect ICpackages to next level interconnection substrates. All these can affectsignal integrity by introducing undesirable changes in impedance andcreating signal reflections. There is also concern about signal skew,cause by differing signal lengths, which is important in assuring propersignal timing.

The first place in an electronic system such parasitic effects areencountered, beyond those encountered within the IC structure itself, isthe IC package which is used to connect the IC die to a next levelinterconnection system. While current generation IC packages arepresently reasonably well suited to meeting current needs, as theelectronics industry moving to ever higher data signaling rates, theformerly minor concerns associated with packages and interconnectionpaths have now reached a level of critical importance.

The net effect of this complex web of interactive elements is that theycollectively combine to make it extremely difficult to predict anddesign for reliable high performance at higher processing speeds.Additionally, at higher processing speeds, parasitic effects and signaldiscontinuities and reflections can contribute to the thermal demandsplaced on a system. Thus, as memory circuit speeds climb, there is needfor new approaches to design of memory package interconnections toovercome the looming and highly complex electrical and thermal problemsassociated with traditional approaches to IC memory packaging.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is best illustrated by way of example, and not byway of limitation, in the figures of the accompanying drawings and inwhich like reference numerals refer to similar elements and in which

FIG. 1 shows an example of prior art;

FIG. 2 shows an example of prior art;

FIG. 3 shows an example of prior art;

FIG. 4 shows an example of prior art;

FIG. 5 shows an embodiment of a memory chip package assembly having astair stepped interconnection layer;

FIG. 6 shows an exploded perspective view of an embodiment of amulti-chip memory package assembly having a stair steppedinterconnection layer;

FIG. 7 show an embodiment of a multi-chip memory package assembly inassembled form with a plurality of discrete base materials havingconductor patterns with I/O contacts which are each bonded to a commonand shared base conductor pattern having its own separate I/O contacts;

FIG. 8 show an embodiment of a multi-chip memory package assembly inassembled form with a continuous base material and having disposed on ita plurality of conductor patterns bonded to (or built up additively in asequential process) a base conductor pattern and having I/O contactshaving a joining material attached;

FIG. 9 shows an embodiment of memory module with multi-chip memorypackages assembled to the surface of the memory module;

FIG. 10 shows an IC die with center bond pads and having selected I/Oterminations redistributed to second locations to provide secondaryterminations;

FIG. 11 shows a perspective view of and embodiment of a portion of astrip package with an enlarged area to provide greater detail;

FIGS. 12 A and B disclose assembled, enlarged, and exploded views of anembodiment of a strip package having bridge circuits which cross thebonding apertures to create a multi drop connection path; and

FIG. 13 A-D show in cross section, partial views of various IC packagestrips embodiments having different interconnection pathwaysconstructions to meet alternative interconnection path requirements.

DETAILED DESCRIPTION

Disclosed herein using descriptions and figures are IC packagestructures having stair step connections for use with memory devices andwhich improve control of the quality of an electronic signal that passesthough a memory chip package and between memory chips. Moreover, thenature of the memory package assembly disclosed offers a structurebetter suited to thermal management than current package designs.

The embodiments disclosed herein address the limitations of currentdesign and manufacturing practices employed in the fabrication ofelectronic memory device and system interconnections and the presentinability of those design and manufacturing practices to address fullyand adequately the needs for improved electronic signal integrity as theelectronic signal transitions between memory chips on an electronicmemory module.

An objective of the present disclosure to describe memory packagestructures which provide direct and uniform controlled impedance acrossthe surface of a memory package by routing high speed signals on acontrolled impedance first layer.

Another objective is to describe a first layer having one or more signalpaths which provides a substantially skew free address line for clockingsignals on the package while routing other signals, such as power andground, on a second stair stepped layer wherein both metal layers areinterconnected to the IC memory die.

It is yet another objective of the present disclosure to describe memorypackage structures which reduce the number of I/O required on thepackage due to the package structure's ability to transmit data directlybetween chips within the package.

It is yet another objective of the present disclosure to describe memorypackage structures which provide for improved thermal dissipation.

The present embodiments offer novel alternative approaches to addressingand meeting the stated objectives thus solving certain problemsassociated with current design approaches. Throughout this disclosure,many specific details are recited which are not essential to make or usethe embodiments described herein. Accordingly, these details are offeredfor purposes of clarity and enablement, and are not intended to limitthe spirit and scope of the embodiments described herein, which includesvariations and equivalent structures and processes. For example, the ICdie (IC chip) is shown in the attached drawings as having two centralrows of bond pads. The depiction of this detail is not intended to limitthe scope or application of IC chips described herein. Alternativeembodiments such as those comprising a single row of bond pads, or morethan two rows of bond pads are fully intended as falling within thescope of the embodiments described herein. The advantages are bestillustrated with figures as show herewith, wherein:

FIG. 1 depicts an embodiment previously disclosed in U.S. patentapplication Ser. No. 10/964,578 (Publication 20050093152). A single chipIC package structure having stair stepped electrical interconnections onmore than one level and interconnected by means of wires.

FIG. 2 depicts an embodiment of a previously disclosed IC packagestructure for interconnecting stacked memory packages having electricalinterconnections on two surfaces and interconnected to a common ICcontact by means of wires, which each connect to a different level andeliminating electrical stubs.

FIG. 3 depicts an embodiment disclosed in U.S. Pat. No. 7,014,472. Amemory module has high speed interconnections traversing the moduleassembly and disposed for interconnections at the distal ends of theassembly. Traditional interconnection(s) are displayed on the bottom ofthe memory module for interconnection to a connector such as a PC boardmounted DIMM connector.

FIG. 4 depicts an embodiment disclosed in U.S. patent application Ser.No. 10/987,187 in the form of a multi chip memory IC package structurein strip form wherein all of the interconnections are disposed on acommon monolithic interconnection substrate in a single metal layer.

FIG. 5 discloses a perspective view of a stair step memory IC packageassembly 500 comprising a first dielectric material layer 502 disposedon top of an IC die 501. A first set of conductors and their respectiveterminations 504 a are arranged along the exposed surface of the firstdielectric layer 502. A second dielectric material layer 503 is disposedon top of the first dielectric layer. A second set of conductors andtheir respective terminations 504 b are arranged along the exposedsurface of the second dielectric layer. The conductors 504 a and 504 binclude a narrow end 504 c for connection to the IC die by means ofinterconnecting bond wires 506, and a flat circular region 504 d forelectrically engaging contact members (not shown) of a next levelinterconnection substrate (not shown). The first elongated aperture 505a is formed in dielectric material layer 502, and a second elongatedaperture 505 b is formed in dielectric layer 503. The two apertures 505a, 505 b are aligned above each other to form a center access areaproviding egress for the bond wires 506 that electrically couple theconductors 504 a, 504 b to their respective termination contacts 507 inthe IC die 501. The outer periphery of the second (upper) aperture 505 bis slightly larger than the outer periphery of the first (lower)aperture 505 a. The enlarged outer periphery of aperture in 505 b servesto expose circuit wire bond terminations on 505 a for wire bonding (orother suitable joining method) which are proximate to the inner edge ofthe aperture on dielectric material layer 502. Bond wires 506 are usedto interconnect the IC die terminations 507 to the circuit terminations504 a and 504 b on dielectric layers 502 and 503 respectively. While thestructure is shown with only two layers of conductors, it is not solimited and more layers may be used if needed or desired. Those familiarwith the art of PCB and IC package manufacture will know that anadditional protective dielectric insulating layer, such as a solder maskor cover layer or by means of a build up polymer layer, is commonlyapplied to circuits leaving only the termination I/O exposed. Forclarity of description this layer is omitted.

FIG. 6 discloses an exploded perspective view of the elements ofconstruction for an embodiment of multi-chip memory IC package assembly,including a plurality of IC die 501 positioned above an assembly supportbase structure (i.e. carrier) 602 which may be either permanent ortemporary. In embodiments wherein the support base structure istemporary, the IC die 501 are removed from the support base 602 at sometime after the first dielectric material layer 502 is bonded to theplurality of IC die 501. In embodiments wherein the support basestructure 602 is a permanent part of the circuit, the IC die 501 areadvantageously bonded to the carrier base.

The support base structure 602 has a plurality of cavities 603 having anappropriate size and shape for receiving respective IC die 501.According to an alternative embodiment, an individual die may be abutteddirectly against an adjacent die within a single cavity formed in thesupport base (carrier) structure 602, thereby eliminating the need forindividual cavities 603 sized to securely receive a respective die. Thedie terminations 507 are arranged in dual lines along the center of eachIC die (501). The dual-path alignment of die terminations 507 shown inFIG. 6 is offered only for example, and more or fewer paths areenvisioned, as well as alternative shapes and alignments of dieterminations, which can include, without limitation, alignments formingcircular or elliptical shapes, spirals, star-shapes, and polygons.

A first dielectric layer 601 has a plurality of apertures 604 (analogousto 505 a), each aperture forming an elongated linear shape configured toprovide access to the dual line formation of the die terminations 507formed on an upper surface of a respective die 501. The apertures,however, may be formed in any shape which will allow for exposure of andaccess to the die terminations 507. Conductors 605 disposed on the uppersurface of the first dielectric layer include narrow conductive traceportions 606 b that either terminate at large circular surface region606 a (analogous to 504 d of FIG. 5), or at the edge of a respectiveaperture 604 formed in the first dielectric layer. Some of theconductors 605 do not have either end terminating at a large circularsurface region 606 a, but remain narrow conductive trace portions 606 bhaving each end terminating at a different aperture, thereby functioningto connect adjacent IC die that are assembled within a common ICpackage. The distal ends of each of the narrow conductive trace portions606 b are oriented around the outer periphery of a respective aperture604 in a predetermined arrangement configured to optimize directconnection between a conductor 605 and its respective die termination507. Wire bonds are used couple the circuit ends of respectiveconductive trace portions to wire bond pads on a respective IC die, asillustrated in various figures herein, including FIGS. 5, 11, 12A and13A. The large circular portions 606 a can be used to accept solderballs (not shown) to facilitate interconnection of at least some of theconductors 605 as arranged on the surface of the first (lower)dielectric layer 601 for to a next level electronic element in thecompleted IC package assembly. It is not essential, however, that everyconductor 605 is coupled to a signal source. Embodiments are envisionedwherein some of the conductors are unused. Similarly, it is notessential that every conductor 504 b of the second dielectric layer(discussed below) be coupled to a signal source.

A plurality of second dielectric (insulating base material) layers 503have elongated apertures 505 b conforming to a shape and location of thearrays of die terminations 507. By making the die terminationsaccessible through the aligned upper and lower apertures 505 b, 604,conductive bond wires can be coupled to respective die terminationsduring fabrication. A second plurality of electrical conductors 504 bare arranged on the surface of the second dielectric layer in apredetermined arrangement to facilitate direct connection between aconductor 504 b and its respective die termination 507. The conductors504 b on the plurality of second dielectric layers are also depicted ashaving a large circular surface region 504 d and a narrow conductivetrace 504 c, as described in FIG. 5. The narrow conductive traceportions of these conductor are oriented around the outer periphery of arespective aperture 505 b in a predetermined arrangement to facilitatedirect connection between a conductor 504 b and its respective dietermination 507.

These upper dielectric layers 503 with circuits 504 b are shown asindividual and discrete circuit structures which are bonded to the basecircuit layer 601. According to a first alternative embodiment, a singlecontiguous dielectric upper layer is disposed atop the lower dialecticlayer 601 and secured by appropriate means. According to anotheralternative embodiment, the upper dielectric layer 503 could befabricated on the base layer 601 using a build up layer or similarprocess. Moreover, while the structure of FIG. 6 is shown with only twoconductive layers (i.e., dielectric layers 601, 503 having conductors605, 504 b disposed thereon), FIG. 6 is offered for illustrativepurposes, and is not intended to limit the appended claims, whichenvision embodiments incorporating any number of conductive layers. Byway of example, in another embodiment, the dielectric layer 601 may havea second metal layer on the side opposite the circuits 605. The secondmetal layer can function as a voltage source layer, a ground referencelayer, or may provide additional circuit traces for select circuitconnections other than ground, providing a micro-strip structure orsequence of signal traces that are configured to exhibit a desiredimpedance value, and/or trace lengths configured to equalize signal pathlengths for select signals, thereby reducing or eliminating signal skewfor select signals.

When the assembly is complete, it may be desirable to remove the supportbase by a suitable means to reduce the height of the completed assemblyat which time an optional thin overmold (not shown) may be applied.

FIG. 7 depicts a perspective view of the elements illustrated anddefined in FIG. 6 in an assembled embodiment 700. The IC die (notvisible) or a plurality of IC dies are disposed within the support basestructure (carrier) 602. As discussed in conjunction with FIG. 6, therespective die may be disposed in individual cavity members, or abuttedagainst each other in a single cavity. The first (lower) dielectric(i.e. insulator) layer 701 is bonded to the top of the IC memory die 501(not shown in FIG. 7, visible in FIG. 6), to the peripheral edges of thecarrier 602, or to both the die and the carrier. In embodiments whereinthe die 501 are not permanently disposed within the carrier 602, thefirst (lower) dielectric layer 701 is bonded to the die only, and not tothe carrier. A plurality of second (upper) dielectric layers 702 arebonded to or otherwise disposed or built up on the top surface of thefirst dielectric layer 701. In all embodiments disclosed herein,circuits of a lower dielectric layer can be coupled to respective ICterminals by bond wire prior to, or subsequent to, the bonding of thenext upper dielectric layer(s) to a lower dielectric layer. Spatiallimitations and manufacturing processes will inform the fabricationprocess of the most advantageous order for performing these respectivesteps. After all bond wires 506 from the various dielectric layers havebeen connected to their respective IC terminals 507 (FIG. 5), theapertures (FIG. 5) are filled with a suitable encapsulant 703. I/Oterminations such as solder balls 704 are visible around the peripheriesof the dielectric layers may be attached to the large circular surfaceregions (504 c in FIG. 5).

FIG. 8 depicts a perspective view of an IC package having a single upperdielectric layer 801 coupled across the top of the lower dielectriclayer 701. A plurality of IC die 501 (visible in FIG. 6) are disposedwithin carrier 602. A lower dielectric strip (i.e. interconnectionsubstrate) 701 is disposed above and coupled or attached to the top ofthe IC memory die, the periphery of the carrier, or both. In embodimentswherein the die 501 are not permanently disposed within the carrier 602,the first (lower) dielectric layer 701 is bonded to the die only, andnot to the carrier. A second (upper) contiguous dielectric strip 801bonded to the top of the first dielectric strip 701. The apertures (notvisible) of the upper and lower dielectric strips are aligned duringfabrication. After the bond wires 506 have been connected to theirrespective IC terminals 507 (FIG. 5), the apertures are filled with asuitable encapsulant 703. I/O terminations such as solder balls 704visible around the peripheries of the dielectric layers may be attachedto the large circular surface regions (504 d in FIG. 5). In theembodiment depicted in FIG. 8, the second (upper) strip 801 is shown asbeing a formed from separate piece that is distinct from, and bonded, tothe lower dielectric strip. However, alternative embodiments areenvisioned wherein the upper dielectric strip is built up on the basecircuit strip using build up layer circuit manufacturing techniques. Thestructure is shown with two circuit layers, each layer having separateconductive circuit pathways on insulating base materials. However, thespecific number of dielectric layers shown in FIG. 8 is intended only asan example, and any number of dielectric layers may be used inconjunction with the embodiments described herein.

FIG. 9 depicts a side elevational view of the assembled multi chipmemory packages 700 of FIG. 7 mounted on and interconnected to a memorymodule 900 such as a DIMM memory card. Centrally located on the moduleis an advanced memory buffer (AMB) package 901 which accesses andaddresses the memory IC packages 700 by way of lateral signal paths 904,while power, ground and other signals for both the memory and AMB chipare accessed in traditional manner by way of conductors 903 connected toedge card terminations 902 on the memory module. The construction of thememory chip packages can be modified as desired to provide direct accessto the AMB.

FIG. 10 shows an embodiment of a complementary cross-path IC die 1000having parallel complementary inner and outer rows of bond pads on theupper surface of a modified IC die. Two parallel inner rows 1001 of bondpads are disposed between two parallel outer rows 1002 of bond pads1002. A conductor path 1003 coupled to a bond pad from the left hand rowof the inner rows 1001 extends to the right, passing between two bondpads of the right hand row of the inner rows 1001, and is coupled to acomplementary bond pad on the right hand row of the outer rows 1002. Aconductor path 1003 coupled to a respective bond pad from the right handrow of the inner rows 1001 extends to the left, passing between two ICterminals in the left hand row of the inner rows 1001, and is coupled toa complementary bond pad on the left hand row of the outer rows 1002.Conductor paths 1003 can be etched, bonded, or otherwise coupled to thesurface of the IC die. Referring to FIGS. 6 and 10, when IC terminals ofadjacent first and second IC die 507 are to be connected by means ofnarrow signal paths 606 b, 605 of FIG. 6, the complementary cross-pathembodiment of FIG. 10 allows any IC terminal on a first IC die to beconnected to any IC terminal on an adjacent IC die. This complementarycross-path structure is therefore useful in IC die utilizing parallel ICterminal arrays. The bond pads 1001, 1002 are coupled to the signalpaths 606 b, 605 by a suitable means such as wire bonding. The signalpath provided through this embodiment can exhibit a variety ofadvantageous design characteristics, such as fewer electrical stubs, ora more optimal signal path length, thereby reducing signal reflection,skew, and other deleterious signal phenomena.

FIG. 11 provides a perspective view and enlargement of a portion of astrip package embodiment 1100 having conductors 1101 disposed along thepackage edges to interconnect directly to an adjacent IC die or IC chipin the strip package (not shown). In the enlargement, noncontiguousconductive traces 1101 are electrically coupled by bond wires 1102 a and1002 b to form a contiguous circuit path 1103 suitable for multi dropinterconnection to adjoining ICs in the strip package.

FIGS. 12A and 12B respectively show an assembled top plan view and anexploded view of an embodiment of a portion of an IC package structure1200. The package assembly includes a first or interior dielectric layer1201 (the lower dielectric layer in FIG. 12B), which is disposed in theinterior of the IC package structure between the IC die 501 and thesecond (upper) dielectric layer 503. The interior dielectric layer has aleft edge 1209, a right edge 1210, and a plurality of apertures 1204arranged in a line along the center portion of the first dielectriclayer. Adjacent apertures 1204 are separated by a dielectric bridge1203, formed from a continuous portion of the first dielectric layerextending across the center portion of the first dielectric layer.According to the linear arrangement of the apertures 1204 on theinterior dielectric layer, for “n” apertures, there are therefore “n−1”dielectric bridges. Conductive paths 1202 extend laterally across thefirst dielectric layer from the left edge 1209 to the right edge 1210allowing connection to adjacent ICs on either side (not shown).Electrical continuity from edge to edge is maintained because each ofthe conductive paths 1202 crosses one of the dielectric bridges 1203,thereby traversing the center section the first dielectric layer.Multiple separate conductive paths, however, can traverse across asingle dielectric path. As discussed in conjunction with the enlargedview, the apertures 1204 between the dielectric bridges allow access tobond pads 507 on the IC die 501 and other connective members duringfabrication of the IC package 1200.

A second (upper) dielectric layer 503 is disposed above the interiordielectric layer, and has a single aperture 504 b extending down thecenter portion of the layer 530. As discussed above, the shape andlocation of apertures on the respective layers is according to thelocation of the bond pads and circuit connection points on an IC die towhich the various dielectric layers are coupled. The size of theapertures is sufficient to grant access to the bond pads and connectionpoints during fabrication, according to the size of the tools used infabrication. Circuit paths 504 b are disposed on the upper surface ofthe upper layer 503. The circuit paths include rounded planar surfaceareas 504 d for interconnection with a next level electronic element,and narrow trace sections 504 c extending to the periphery of theaperture 504 b and oriented in predetermined positions forinterconnection with respective terminals on the IC die.

The enlarged view above FIG. 12 A provides greater detail of certainstructures in FIGS. 12A and B. The wire bond termination 1204 ondielectric layer 1201. The larger aperture 505 b of dielectric layer 503is identified by peripheral edges 1207 a 1207 b. The two bond wires 506in the upper portion of the enlarged view form wire bond connectionsfrom select IC die bond pads 507 to respective circuit terminations 504d on the upper dielectric layer 503. The two bond wires 506 in the lowerportion of the enlarged view form wire bond connections from select ICdie bond pads 507 to conductive circuit terminations 1202 a on the lowerdielectric layer 1201. The surface of dielectric layer 1201 is seenextending across the aperture from the right peripheral edge 1208A tothe left peripheral edge 1208B to form a dielectric bridge 1203, andcircuits 1202 disposed on the surface of dielectric layer 1201 are seenon the dielectric bridge 1203, thereby allowing these circuit paths totraverse the aperture 1204.

Returning briefly to FIG. 12A, an encapsulant 703 is disposed within thecavity formed by the aligned apertures. It is shown open at the upperend to expose detail for enlargement. According to a preferredfabrication embodiment, the encapsulant 703 is not deposited in thecenter cavity until the interior dielectric layer 1201 has been bondedto the IC die 501, the second dielectric layer 503 has been bonded tothe interior dielectric layer 1201, and all required bond wires havebeen secured to their respective terminals and connection points.

FIGS. 13 A-13D show in cross section, partial views of various IC diepackage strip embodiments having different interconnection pathwayconstructions to meet alternative interconnection path requirements.While the various embodiments are all illustrated with two metal layers(conductive paths disposed on one surface of each of two layereddielectric substrates), this specific number of layers is offered onlyfor example, and embodiments can be utilized with any number of metallayers. For example, an additional conductive layer, disposed either onthe top or bottom side of the IC die as oriented in FIGS. 13A-13D, couldbe used as a ground layer with transmission paths having a predeterminedimpedance, or a predetermined path length, and thereby configured toreduce signal reflection, signal skew, or counter other transmissioneffects that erode signal integrity.

In FIG. 13A, an IC die 1301 is depicted with two circuit layers disposedthereupon. The first layer comprises a first dielectric (insulating)layer 1302 with a bottom surface bonded to the IC die. Conductive paths1303 a, 1303 b are etched, or otherwise disposed upon the top surface ofthe first layer dielectric layer 1302 a. The second layer comprises asecond dielectric layer 1302 b having a bottom surface affixed to thetop surface of the first layer, and conductive paths 1304 a, 1304 bformed on the upper surface of the second dielectric layer 1302 b. Thecross sectional view discloses IC terminations 1306 disposed on thesurface of the IC die 1301 within the apertures a and a′ and moreclearly shows the inner edges of the first (lower) dielectric layer 1302extending horizontally further toward the center of the aperture thanthe inner edges of the second (upper) dielectric layer 1302 b, therebycreating a tapered or stair-step effect around the cavity formed byapertures a and a′ A wire bond 1305 is used to connect from wire bondterminations 1306 on the IC 1301 to the conductors. Phantom bond wires1307 are illustrated to represent bond wires connected to other bondpads and other connections on other layers. The assembly is shown withan encapsulant 1308 to protect the wire bonds after assembly.

Owing to the limitations of space in FIGS. 13A-13D, many elements thatare known to those skilled in the art have been omitted from theseFigures, including, but not limited to, protective insulation onconductive paths 1304 a and 1304 b, or solder balls or other joiningmaterial used to electrically couple the bond wires to specificconductive terminals. The omission of these, and other elements fromvarious Figures described herein has been done to reduce visual clutterand enhance illustrative clarity. Accordingly, the omission of such wellknown structural elements from select Figures is not intended to limitthe scope of the embodiments described herein, or of the appendedclaims.

FIG. 13B shows in a cross section view substantially the embodimentshown in FIG. 11 wherein a conductive path 1309 is interconnected to afirst termination point (i.e. bond pad) 1307 on the IC chip 1301 and toa second termination point (e.g bond pad) 1310 completing a circuitacross the IC die between wire bonds to first layer circuits 1303 a and1303 b.

FIG. 13C shows in a cross section view what is substantially theembodiment shown in FIG. 12, wherein a conductive circuit pathway 1311is continuous and bridges and traverses above the chip but is alsointerconnected to the native chip termination 1307 to provide a multidrop connection path.

FIG. 13 D shows in a cross section a view of an embodiment whereinredistribution circuits 1312 a and 1312 b are provided on the surface ofthe IC die 1301 and are interconnected to a first termination point(i.e. bond pad) 1307 on the IC die 1301 disposed beneath theredistribution circuits, and interconnected to circuit paths 1314 a and1314 b above the redistribution circuits by second termination members1313 a and 1313 b representing any suitable connection means, such asany of several flip chip bonding methods.

Restating here for emphasis, while the structures illustrated in thisdisclosure have shown with wire bonds being made to two rows of centralbond pads on the IC die, the structures are not so limited and couldalso be used for created using a single bond pad in the center of the ICdie or at the edges of the IC die or combinations thereof.

Although the invention has been described briefly with reference tospecific exemplary embodiments thereof, it will be evident that variousmodifications and changes may be made thereto without departing from thebroader spirit and scope of the invention as set forth in the appendedclaims. Moreover, many specific details have been included herein whichare not essential to make and use every embodiment of the invention.These details have been included to assist the reader in more easilyunderstanding and comprehending the embodiments described herein.Accordingly, the specification and drawings of this disclosure should beregarded in an illustrative rather than a restrictive sense.

1-10. (canceled)
 11. An electrical assembly comprising: a first IC memory package with a first plurality of memory dies including a first memory die, each memory die having an active surface with a plurality of die terminals disposed thereon, the first memory die having a first die terminal in electrical continuity with first and second die bond-pads formed on the active surface.
 12. The electrical assembly of claim 11 wherein a surface region of the first die terminal is coextensive with at least part of a surface region of the first die bond-pad.
 13. The electrical assembly of claim 11 wherein the first die bond-pad and second die-bond pad are electrically coupled, at least in part, by a signal trace.
 14. The electrical assembly of claim 13 wherein the signal trace is formed on the active surface of the first memory die.
 15. The electrical assembly of claim 11, the first IC memory package further comprising: a first dielectric layer with an active surface having a first plurality of circuit traces disposed thereupon, including a first circuit trace, the first plurality of circuit traces having first and second terminal ends; and, a first bond wire with a first end coupled to the first circuit trace and a second end coupled with the first die bond-pad.
 16. The electrical assembly of claim 15 further comprising a second wire bond coupling the second die bond-pad to a second circuit trace.
 17. The electrical assembly of claim 16 wherein the first dielectric layer comprises a back surface coupled to the active surfaces of the first plurality of memory dies.
 18. The electrical assembly of claim 17, wherein the first dielectric layer comprises a first plurality of apertures configured to expose at least some of the die bond-pads on the active surfaces of the first plurality of memory dies.
 19. The electrical assembly of claim 18 further comprising a second dielectric layer with an active surface and a back surface, the active surface having a second plurality of circuit traces disposed thereupon, each of the second plurality of circuit traces having first and second ends, wherein the back surface of the second dielectric layer is coupled to the active surface of the first dielectric layer.
 20. The electrical assembly of claim 19 wherein the second dielectric layer covers at least a portion of some of the first plurality of signal traces, the second dielectric layer comprising a second plurality of apertures configured in a stair step arrangement with at least some of the first plurality of apertures, and wherein the second plurality of apertures are configured to expose the first end of at least some of the first plurality of circuit traces.
 21. The electrical assembly of claim 20 wherein the second plurality of circuit traces includes the second circuit trace.
 22. The electrical assembly of claim 20 wherein the first plurality of circuit traces includes the second circuit trace.
 23. The electrical assembly of claim 11, wherein the first plurality of memory dies are disposed on a first carrier.
 24. The electrical assembly of claim 23 wherein the first carrier comprises a plurality of cavities, and wherein the first memory die is disposed in a first cavity, and the second memory die is disposed in a second cavity.
 25. The electrical assembly of claim 23 wherein an edge of a first memory die in the first IC memory package abuts an edge of a second memory die in the first IC memory package.
 26. The electrical assembly of claim 11 further comprising: a printed circuit board wherein said first IC memory package is mounted on the printed circuit board; a plurality of edge connector terminals disposed along at least one edge of the printed circuit board; a second IC memory package mounted on the printed circuit board, wherein the first and second IC memory packages are electrically coupled to the edge connector terminals on the printed circuit board.
 27. The electrical assembly of claim 26 further comprising: an advanced memory buffer mounted on the printed circuit board and electrically coupled to the first and second IC memory packages.
 28. An electrical assembly with a first IC memory package, the first IC memory package comprising: a first memory die having an active surface with a plurality of die bond pads disposed thereon, including first and second die bond pads a first dielectric layer having a back surface disposed against the active surface of the first memory die, and an active surface with a first plurality of circuit traces disposed thereon, including a first circuit trace with first and second terminal ends configured to couple with corresponding conductive members; and, a first bond wire with a first end coupled to the first die bond pad and a second end coupled to a first section of the first circuit trace between the first and second terminal ends.
 29. The electrical assembly of claim 28, wherein the first dielectric layer comprises a first aperture exposing the first die bond pad and a second aperture exposing the second die bond pad, the first and second apertures being separated by a first dielectric bridge, wherein the first circuit trace spans the first dielectric bridge.
 30. The electrical assembly of claim 29, wherein the first memory die comprises two parallel rows of die bond pads, including a third die bond pad adjacent the first die bond pad and exposed by the first aperture, and a fourth die bond pad adjacent the second die bond pad and exposed by the second aperture.
 31. The electrical assembly of claim 30, wherein the first plurality of circuit traces further comprises a second circuit trace with first and second terminal ends, the first IC memory package further comprising a second bond wire with a first end coupled with the fourth die bond pad and a second end coupled with a first section of the second circuit trace between the first and second terminal ends.
 32. The electrical assembly of claim 31, wherein the second circuit trace spans the first dielectric bridge abreast the first circuit trace.
 33. The electrical assembly of claim 32, wherein the first dielectric layer further comprises third and fourth apertures separated by a second dielectric bridge, the third and fourth apertures exposing respective third and fourth die bond pads disposed on the active surface of the second memory die.
 34. The electrical assembly of claim 33, wherein the first circuit trace further spans the second dielectric bridge.
 35. The electrical assembly of claim 34, the first IC memory package further comprising a second bond wire with a first end coupled to the first circuit trace, and a second end coupled to the third die bond pad.
 36. The electrical assembly of claim 29, the first IC memory package further comprising: a second dielectric layer with a back surface disposed against the active surface of the first dielectric layer, and an active surface that has a second plurality of conductive circuit traces disposed thereon, including a second circuit trace; and, a second bond wire electrically coupled from the second die bond pad to the second circuit trace.
 37. The electrical assembly of claim 36, wherein the second dielectric surface comprises a third aperture disposed above, and in stair step relationship with the first and second apertures.
 38. The electrical assembly of claim 34, the first IC memory package further comprising a third memory die with an active surface having a plurality of die bond pads, including a fifth die bond pad electrically coupled to the first circuit trace by a wire bond.
 39. The electrical assembly of claim 26 wherein the first circuit trace has a first end engaging a first conductive member of a next level electrical component, a second end engaging a second conductive member of a next level electrical component, and wherein the first bond wire is coupled to the first circuit trace between the first and second ends.
 40. The electrical assembly of claim 39 wherein the first IC memory package is mounted on a memory card having edge connection terminals, the electrical assembly further comprising: an advanced memory buffer mounted on the memory card and electrically coupled with the first IC memory package; and, a second IC memory package mounted on the memory card and electrically coupled with the advanced memory buffer.
 41. An electrical assembly with a first IC memory package, the first IC memory package comprising: a plurality of memory dies including first and second memory dies, each memory die having an active surface that has at least three parallel rows of die bond pads, including first and second outer rows, and a third inner row disposed between the outer rows; a first dielectric layer with an active surface that has a first plurality of circuit traces disposed thereon, including first and second circuit traces, wherein the active surface of the first dielectric layer faces the active surface of the first memory die, and wherein a first die bond terminal in the first outer row is coupled to the first circuit trace by a conductive bump, and a second die bond terminal in the second outer row is coupled to the second circuit trace by a second conductive bump.
 42. The electrical assembly of claim 41 further comprising a second dielectric layer with a back surface coupled to the first dielectric layer, and an active surface with a second plurality of circuit traces disposed thereon, including a third signal trace.
 43. The electrical assembly of claim 42 further comprising a bond wire with a first end coupled to a die bond pad in the third row of die bond pads, and a second end coupled to the third signal trace.
 44. The electrical assembly of claim 41 wherein the plurality of memory dies are disposed on a carrier.
 45. The electrical assembly of claim 44 wherein the carrier comprises a plurality of cavities, and wherein the first memory die is disposed in a first cavity, and the second memory die is disposed in a second cavity.
 46. The electrical assembly of claim 44 wherein an edge of a first memory die in the first IC memory package abuts an edge of the second memory die in the first IC memory package.
 47. The electrical assembly of claim 41 wherein the first IC memory package is mounted on a memory card having edge connection terminals, the electrical assembly further comprising: an advanced memory buffer mounted on the memory card and electrically coupled with the first IC memory package; and, a second IC memory package mounted on the memory card and electrically coupled with the advanced memory buffer. 